ABSTRACT

Techniques for Optimizing Multiprocessor Implementations of Signal Processing Applications

An indispensable component of the information age, signal processing is embedded in a variety of consumer devices, including cell phones and digital television, as well as in communication infrastructure, such as media servers and cellular base stations. Multiple programmable processors, along with custom hardware running in parallel, are needed to achieve the computation throughput required of such applications.

Reviews important research in key areas related to the multiprocessor implementation of multimedia systems
Embedded Multiprocessors: Scheduling and Synchronization, Second Edition presents architectures and design methodologies for parallel systems in embedded digital signal processing (DSP) applications. It discusses application modeling techniques for multimedia systems, the incorporation of interprocessor communication costs into multiprocessor scheduling decisions, and a modeling methodology (the synchronization graph) for multiprocessor system performance analysis. The book also applies the synchronization graph model to develop hardware and software optimizations that can significantly reduce the interprocessor communication overhead of a given schedule.

Chronicles recent activity dealing with single-chip multiprocessors and dataflow models
This edition updates the background material on existing embedded multiprocessors, including single-chip multiprocessors. It also summarizes the new research on dataflow models for signal processing that has been carried out since the publication of the first edition.

Harness the power of multiprocessors
This book explores the optimization of interprocessor communication and synchronization in embedded multiprocessor systems. It shows you how to design multiprocessor computer systems that are streamlined for multimedia applications.

chapter 1|12 pages

INTRODUCTION

chapter 2|22 pages

APPLICATION-SPECIFIC MULTIPROCESSORS

chapter 3|24 pages

BACKGROUND TERMINOLOGY AND NOTATION

chapter 5|20 pages

MULTIPROCESSOR SCHEDULING MODELS

chapter 6|26 pages

IPC-CONSCIOUS SCHEDULING ALGORITHMS

chapter 7|34 pages

THE ORDERED-TRANSACTIONS STRATEGY

chapter 9|16 pages

EXTENDING THE OMA ARCHITECTURE

chapter 10|36 pages

SYNCHRONIZATION IN SELF-TIMED SYSTEMS

chapter 11|32 pages

RESYNCHRONIZATION

chapter 12|46 pages

LATENCY-CONSTRAINED RESYNCHRONIZATION

chapter 13|6 pages

INTEGRATED SYNCHRONIZATION OPTIMIZATION

chapter 14|4 pages

FUTURE RESEARCH DIRECTIONS